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FEATURES Optimally Compensated Active Voltage Positioning with Gain and Offset Adjustment (ADOPTTM) for Superior Load Transient Response Complies with VRM 8.4 Specifications with Lowest System Cost 4-Bit Digitally Programmable 1.3 V to 2.05 V Output N-Channel Synchronous Buck Driver Two On-Board Linear Regulator Controllers Total Accuracy 0.8% Over Temperature High Efficiency Current-Mode Operation Short Circuit Protection Power Good Output Overvoltage Protection Crowbar Protects Microprocessors with No Additional External Components APPLICATIONS Core Supply Voltage Generation for: Intel Pentium(R) III Intel CeleronTM
4-Bit Programmable Synchronous Buck Controllers ADP3159/ADP3179
FUNCTIONAL BLOCK DIAGRAM
VCC CT
ADP3159/ADP3179
UVLO & BIAS OSCILLATOR SET RESET CROWBAR REFERENCE GND DAC+20% VLR1 LRFB1 LRDRV1 VLR2 LRFB2 LRDRV2 gm COMP REF VID DAC CMP -+ CS+ FB PWRGD REF PWM DRIVE DRVL DRVH
DAC-20% CS-
VID3
VID2
VID1
VID0
GENERAL DESCRIPTION
The ADP3159 and ADP3179 are highly efficient output synchronous buck switching regulator controllers optimized for converting a 5 V main supply into the core supply voltage required by high-performance processors. These devices use an internal 4-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 1.3 V and 2.05 V. They use a current mode, constant off-time architecture to drive two N-channel MOSFETs at a programmable switching frequency that can be optimized for regulator size and efficiency. The ADP3159 and ADP3179 also use a unique supplemental regulation technique called Analog Devices Optimal Positioning Technology (ADOPT) to enhance load transient performance. Active voltage positioning results in a dc/dc converter that meets the stringent output voltage specifications for high-performance processors, with the minimum number
of output capacitors and smallest footprint. Unlike voltagemode and standard current-mode architectures, active voltage positioning adjusts the output voltage as a function of the load current so it is always optimally positioned for a system transient. The devices also provide accurate and reliable short circuit protection and adjustable current limiting. They also include an integrated overvoltage crowbar function to protect the microprocessor from destruction in case the core supply exceeds the nominal programmed voltage by more than 20%. The ADP3159 and ADP3179 contain two fixed-output voltage linear regulator controllers that are designed to drive external N-channel MOSFETs. The outputs are internally fixed at 2.5 V and 1.8 V in the ADP3159, while the ADP3179 provides adjustable output, which is set using an external resistor divider. These linear regulators are used to generate the auxiliary voltages (AGP, GTL, etc.) required in most motherboard designs, and have been designed to provide a high bandwidth load-transient response. The ADP3159 and ADP3179 are specified over the commercial temperature range of 0C to 70C and are available in a 20-lead TSSOP package.
ADOPT is a trademark of Analog Devices, Inc. Pentium is a registered trademark of Intel Corporation. Celeron is a trademark of Intel Corporation.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
ADP3159/ADP3179-SPECIFICATIONS1 (VCC = 12 V, T = 0 C to 70 C, unless otherwise noted.)
A
Parameter FEEDBACK INPUT Output Accuracy 1.3 V Output 1.65 V Output 2.05 V Output Line Regulation Crowbar Trip Point Crowbar Reset Point Crowbar Response Time VID INPUTS Input Low Voltage Input High Voltage Input Current Pull-Up Resistance Internal Pull-Up Voltage OSCILLATOR Off Time CT Charge Current ERROR AMPLIFIER Output Resistance Transconductance Output Current Maximum Output Voltage Output Disable Threshold -3 dB Bandwidth CURRENT SENSE Threshold Voltage Input Bias Current Response Time OUTPUT DRIVERS Output Resistance Output Transition Time LINEAR REGULATORS Feedback Current LR1 Feedback Voltage LR2 Feedback Voltage Driver Output Voltage POWER GOOD COMPARATOR Undervoltage Threshold Undervoltage Hysteresis Overvoltage Threshold Overvoltage Reset Point Output Voltage Low Response Time SUPPLY DC Supply Current2 UVLO Threshold Voltage UVLO Hysteresis
Symbol VFB
Conditions
Min
Typ
Max
Unit
VOUT VCROWBAR tCROWBAR VIL(VID) VIH(VID) IVID RVID
Figure 1 Figure 1 Figure 1 VCC = 10 V to 14 V % of Nominal DAC Voltage % of Nominal DAC Voltage Overvoltage to DRVL Going High
1.289 1.637 2.034 115 40
1.3 1.65 2.05 0.06 120 50 400
1.311 V 1.663 V 2.066 V % 125 % 60 % ns 0.6 V V A k V s A A m mmho A V mV kHz mV mV mV A ns
2.0 VID(X) = 0 V 20 5.0 TA = 25C, CT = 200 pF TA = 25C, VOUT in Regulation TA = 25C, VOUT = 0 V 3.5 130 25 185 30 5.4 4.0 150 35 1 2.2 625 3.0 750 500 78 45 1 0.5 50 250 5.7 4.5 170 45
ICT
RO(ERR) gm(ERR) FB- Forced to VOUT - 3% IO(ERR) VCOMP(MAX) FB- Forced to VOUT - 3% VCOMP(OFF) BWERR COMP = Open VCS(TH) ICS+, ICS- tCS FB- Forced to VOUT - 3% FB- 0.45 V 0.8 V COMP 1 V CS+ = CS- = VOUT CS+ - (CS-) > 87 mV to DRVH Going Low IL = 50 mA CL = 3000 pF
2.05 600
2.35 900
69 35
87 54 5 5
RO(DRV(X)) t R , tF ILRFB(X) VLRFB(1) VLRFB(2) VLRDRV(X) VPWRGD(UV) VPWRGD(OV) VOL(PWRGD)
6 80 0.3 2.5 1.0 1.8 1.0 1 2.56 1.03 1.85 1.03
ns A V V V V V % % % % mV ns mA V V
ADP3159 Figure 2, VCC = 4.5 V to 12.6 V ADP3179 Figure 2, VCC = 2-4.5 V to 12.6 V ADP3159 Figure 2, VCC = 4.5 V to 12.6 V ADP3179 Figure 2, VCC = 2-4.5 V to 12.6 V VCC = 4.5 V, VLRFB(X) = 0 V % of Nominal DAC Voltage % of Nominal DAC Voltage % of Nominal DAC Voltage % of Nominal DAC Voltage IPWRGD(SINK) = 1 mA
2.44 0.97 1.75 0.97 4.2 75 115 40
80 5 120 50 250 250 7 7 1
85 125 60 500
ICC VUVLO
6.75 0.8
9 7.25 1.2
NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2 Dynamic supply current is higher due to the gate charge being delivered to the external MOSFETs. Specifications subject to change without notice.
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REV. A
ADP3159/ADP3179
ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +15 V DRVH, DRVL, LRDRV1, LRDRV2 . . . . -0.3 V to VCC + 0.3 V All Other Inputs and Outputs . . . . . . . . . . . . -0.3 V to +10 V Operating Ambient Temperature Range . . . . . . . 0C to 70C Operating Junction Temperature . . . . . . . . . . . . . . . . . 125C Storage Temperature Range . . . . . . . . . . . . -65C to +150C JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143C/W Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
*This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. Unless otherwise specified, all voltages are referenced to GND.
Pin
Mnemonic
Function
PIN CONFIGURATION RU-20
NC 1 VID0 2 VID1 3 VID2 4 VID3 5 PWRGD 6
20 GND 19 NC 18 DRVH 17 DRVL
ADP3159/ ADP3179
16 VCC
TOP VIEW 15 LRFB2 (Not to Scale) 14 LRDRV2 LRFB1 7
13 COMP 12 CT 11 CS+
LRDRV1 8 FB 9 CS- 10
NC = NO CONNECT
1, 19 NC No Connection. 2-5 VID3, VID2, Voltage Identification DAC Inputs. These VID1, VID0 pins are pulled up to an internal reference, providing a Logic One if left open. The DAC output programs the FB regulation voltage from 1.3 V to 2.05 V. 6 PWRGD Open drain output that signals when the output voltage is in the proper operating range. 7, 15 LRFB1, Feedback connections for the linear LRFB2 regulator controllers. 8, 14 LRDRV1, Gate drives for the respective linear LRDRV2 regulator N-channel MOSFETs. 9 FB Feedback Input. Error amplifier input for remote sensing of the output voltage. 10 CS- Current Sense Negative Node. Negative input for the current comparator. 11 CS+ Current Sense Positive Node. Positive input for the current comparator. The output current is sensed as a voltage at this pin with respect to CS-. 12 CT External capacitor connected from CT to ground sets the Off-time of the device. 13 COMP Error Amplifier Output and Compensation Point. The voltage at this output programs the output current control level between CS+ and CS-. 16 VCC Supply Voltage for the device. 17 DRVL Low-Side MOSFET Drive. Gate drive for the synchronous rectifier N-channel MOSFET. The voltage at DRVL swings from GND to VCC. 18 DRVH High-side MOSFET Drive. Gate drive for the buck switch N-channel MOSFET. The voltage at DRVH swings from GND to VCC. 20 GND Ground Reference. GND should have a low impedance path to the source of hte synchronous MOSFET.
ORDERING GUIDE
Model ADP3159JRU ADP3179JRU
Temperature Range 0C to 70C 0C to 70C
LDO Voltage 2.5 V, 1.8 V Adjustable
Package Description Thin Shrink Small Outline Thin Shrink Small Outline
Package Option RU-20 RU-20
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3159 and the ADP3179 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
-3-
ADP3159/ADP3179 -Typical Performance Characteristics
TEK RUN 60 TRIG'D
50
SUPPLY CURRENT - mA
40 VCC 30
1
20
10
2
VCORE
0 0 100 200 300 400 500 600 700 800 OSCILLATOR FREQUENCY - kHz
CH1 5.00V B W CH2
500mV BW M 10.0ms A CH1 0.00000 s
5.90V
TPC 1. Supply Current vs. Operating Frequency Using MOSFETs of Figure 3
TPC 4. Power-On Start-Up Waveform
TEK RUN
TRIG'D
25 TA = 25 C VOUT = 1.65V 20
DRVH
NUMBER OF PARTS - %
15
1
10
DRVL
5
CH1 5.00V B W CH2
5.00V BW M 1.00 s A CH1 -2.6500 s
5.90V
0 -0.5
0 OUTPUT ACCURACY - % of Nominal
0.5
TPC 2. Gate Switching Waveforms Using MOSFETs of Figure 3
TPC 5. Output Accuracy Distribution
TEK RUN
TRIG'D
DRVH
DRVL
CH1 2.00V BW CH2
2.00V BW M 1.00ns A CH1 150.000 s
5.88V
TPC 3. Driver Transition Waveforms Using MOSFETs of Figure 3
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REV. A
ADP3159/ADP3179
ADP3159/ ADP3179
1 2 3
NC VID0 VID1 VID2 VID3 PWRGD LRFB1 LRDRV1 FB CS-
GND 20 NC 19 DRVH 18 DRVL 17 VCC 16 LRFB2 15 LRDRV2 14 COMP 13 CT 12 CS+ 11 100 100nF AD820 + 1F 12V 100nF
4-BIT CODE
4 5 6 7 8
VFB
9 10
Analog Devices Optimal Positioning Technology (ADOPT) adjusts the output voltage as a function of the load current so that it is always optimally positioned for a load transient. Standard (passive) voltage positioning, sometimes recommended for use with other architectures, has poor dynamic performance which renders it ineffective under the stringent repetitive transient conditions specified in Intel VRM documents. Consequently, such techniques do not allow the minimum possible number of output capacitors to be used. ADOPT, as used in the ADP3159 and ADP3179, provides a bandwidth for transient response that is limited only by parasitic output inductance. This yields optimal load transient response with the minimum number of output capacitors.
Cycle-by-Cycle Operation
NC = NO CONNECT
1.2V
Figure 1. Closed Loop Output Voltage Accuracy Test Circuit
ADP3159/ ADP3179
1 2 3 4 5 6
NC VID0 VID1 VID2 VID3 PWRGD LRFB1 LRDRV1 FB CS-
GND 20 NC 19 DRVH 18 DRVL 17 VCC 16 LRFB2 15 LRDRV2 14 COMP 13 CT 12 CS+ 11 10nF VLR2 + 1F VCC 100nF
VLR1
7 8
10nF
9 10
NC = NO CONNECT
Figure 2. Linear Regulator Output Voltage Accuracy Test Circuit
THEORY OF OPERATION
During normal operation (when the output voltage is regulated), the voltage error amplifier and the current comparator are the main control elements. During the on-time of the high-side MOSFET, the current comparator monitors the voltage between the CS+ and CS- pins. When the voltage level between the two pins reaches the threshold level, the DRVH output is switched to ground, which turns off the high-side MOSFET. The timing capacitor CT is then charged at a rate determined by the off-time controller. While the timing capacitor is charging, the DRVL output goes high, turning on the low-side MOSFET. When the voltage level on the timing capacitor has charged to the upper threshold voltage level, a comparator resets a latch. The output of the latch forces the low-side drive output to go low and the high-side drive output to go high. As a result, the low-side switch is turned off and the high-side switch is turned on. The sequence is then repeated. As the load current increases, the output voltage starts to decrease. This causes an increase in the output of the voltage-error amplifier, which, in turn, leads to an increase in the current comparator threshold, thus tracking the load current. To prevent cross conduction of the external MOSFETs, feedback is incorporated to sense the state of the driver output pins. Before the low-side drive output can go high, the high-side drive output must be low. Likewise, the high-side drive output is unable to go high while the low-side drive output is high.
Power Good
The ADP3159 and ADP3179 use a current-mode, constant off-time control technique to switch a pair of external N-channel MOSFETs in a synchronous buck topology. Constant off-time operation offers several performance advantages, including that no slope compensation is required for stable operation. A unique feature of the constant off-time control technique is that since the off-time is fixed, the converter's switching frequency is a function of the ratio of input voltage to output voltage. The fixed off-time is programmed by the value of an external capacitor connected to the CT pin. The on-time varies in such a way that a regulated output voltage is maintained as described below in the cycle-by-cycle operation. The on-time does not vary under fixed input supply conditions, and it varies only slightly as a function of load. This means that the switching frequency remains fairly constant in a standard computer application.
Active Voltage Positioning
The ADP3159 has an internal monitor that senses the output voltage and drives the PWRGD pin of the device. This pin is an open drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage has been within a 20% regulation band of the targeted value for more than 500 ms. The PWRGD pin will go low if the output is outside the regulation band for more than 500 ms.
Output Crowbar
The output voltage is sensed at the CS- pin. A voltage error amplifier, (gm), amplifies the difference between the output voltage and a programmable reference voltage. The reference voltage is programmed to between 1.3 V and 2.05 V by an internal 4-bit DAC that reads the code at the voltage identification (VID) pins (Refer to Table I for output voltage vs. VID pin code information). A unique supplemental regulation technique called REV. A
An added feature of using an N-channel MOSFET as the synchronous switch is the ability to crowbar the output with the same MOSFET. If the output voltage is 20% greater than the targeted value, the controller IC will turn on the lower MOSFET, which will current-limit the source power supply or blow its fuse, pull down the output voltage, and thus save the microprocessor from destruction. The crowbar function releases at approximately 50% of the nominal output voltage. For example, if the output is programmed to 1.5 V, but is pulled up to 1.85 V or above, the crowbar will turn on the lower MOSFET. If in this case the output is pulled down to less than 0.75 V, the crowbar will release, allowing the output voltage to recover to 1.5 V if the fault condition has been removed. -5-
ADP3159/ADP3179
D2 MBR052LT1 5V STANDBY D3 MBR052LT1 12V C6 1F + C7 22 F Q4 SUB45N03-13L L1 1.7 H + C8 1000 F L2 1H + C9 1000 F 5V
ADP3159/ ADP3179 U1 GND 20 1 NC
5V FROM CPU 2 VID0 3 VID1 4 VID2 5 VID3 POWER GOOD 3.3V C15 1F Q1 SUB45N03-13L NC = NO CONNECT VLR1 2.5V, 2A C2 68pF 6 PWRGD 7 LRFB1 8 LRDRV1 9 FB 10 CS- NC 19 DRVH 18 DRVL 17 VCC 16 LRFB2 15 LRDRV2 14 COMP 13 CT 12 CS+ 11 C4 2.7nF R7 10.5k C3 150pF C10 1nF R8 78.7k C11 68pF 3.3V
R12 4m +
1000 Fx5 24m (EACH) + + + +
R1 10k
Q3 SUB75N03-07
VCC CORE 1.30V TO 2.05V 15A
C17 C18 C19 C20 C21
C16 1F Q2 SUB45N03-13L
R11 10k
R2 10k
C1 100 F
+
R4 220 R3 220
+ C5 100 F
VLR2 1.8V, 2A
Figure 3. 15 A Pentium III Application Circuit
On-board Linear Regulator Controllers
The ADP3159 and ADP3179 include two linear regulator controllers to provide a low cost solution for generating additional supply rails. In the ADP3159, these regulators are internally set to 2.5 V (LR1) and 1.8 V (LR2) with 2.5% accuracy. The ADP3179 is designed to allow the outputs to be set externally using a resistor divider. The output voltage is sensed by the high input impedance LRFB(x) pin and compared to an internal fixed reference. The LRDRV(x) pin controls the gate of an external N-channel MOSFET resulting in a negative feedback loop. The only additional components required are a capacitor and resistor for stability. Higher output voltages can be generated by placing a resistor divider between the linear regulator output and its respective LRFB pin. The maximum output load current is determined by the size and thermal impedance of the external power MOSFET that is placed in series with the supply and controlled by the ADP3159. The linear regulator controllers have been designed so that they remain active even when the switching controller is in UVLO mode to ensure that the output voltages of the linear regulators will track the 3.3 V supply as required by Intel design specifications. By diode ORing the VCC input of the IC to the 5 VSB and 12 V supplies as shown in Figure 3, the switching output will be disabled in standby mode, but the linear regulators will begin conducting once VCC rises above about 1 V. During
start-up the linear outputs will track the 3.3 V supply up until they reach their respective regulation points, regardless of the state of the 12 V supply. Once the 12 V supply has exceeded the 5 VSB supply by more than a diode drop, the controller IC will track the 12 V supply. Once the 12 V supply has risen above the UVLO value, the switching regulator will begin its start-up sequence.
Table I. Output Voltage vs. VID Code
VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
VOUT(NOM) 1.30 V 1.35 V 1.40 V 1.45 V 1.50 V 1.55 V 1.60 V 1.65 V 1.70 V 1.75 V 1.80 V 1.85 V 1.90 V 1.95 V 2.00 V 2.05 V
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REV. A
ADP3159/ADP3179
APPLICATION INFORMATION Specifications for a Design Example
RSENSE is the resistance of the sense resistor (estimated value: 4 m) RL is the resistance of the inductor (estimated value: 3 m)
Inductance Selection
The design parameters for a typical 750 MHz Pentium III application (shown in Figure 3) are as follows: Input Voltage: (VIN) = 5 V Auxiliary Input: (VCC) = 12 V Output Voltage (VVID) = 1.7 V Maximum Output Current (IO(MAX)) = 15 A Minimum Output Current (IO(MIN)) = 1 A Static tolerance of the supply voltage for the processor core (VO) = +40 mV (-80 mV) = 120 mV Transient tolerance (for less than 2 s) of the supply voltage for the processor core when the load changes between the minimum and maximum values with a di/dt of 20 A/s (VO(TRANSIENT)) = +80 mV (-130 mV) = 210 mV Input current di/dt when the load changes between the minimum and maximum values < 0.1 A/s. The above requirements correspond to Intel's published power supply requirements based on VRM 8.4 guidelines.
CT Selection for Operating Frequency
The choice of inductance determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and the conduction losses in the MOSFETs, but allows using smaller-size inductors and, for a specified peak-to-peak transient deviation, output capacitors with less total capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses, but requires larger-size inductors and more output capacitance for the same peak-to-peak transient deviation. The following equation shows the relationship between the inductance, oscillator frequency, peak-to-peak ripple current in an inductor and input and output voltages.
L=
VOUT x tOFF IL ( RIPPLE )
(4)
The ADP3159 uses a constant off-time architecture with tOFF determined by an external timing capacitor CT. Each time the high-side N-channel MOSFET switch turns on, the voltage across CT is reset to 0 V. During the off-time, CT is discharged by a constant current of 150 A. Once CT reaches 3.0 V, a new on-time cycle is initiated. The value of the off-time is calculated using the continuous-mode operating frequency. Assuming a nominal operating frequency (fNOM) of 200 kHz at an output voltage of 1.7 V, the corresponding off-time is: V 1 tOFF = 1 - OUT x VIN fNOM 1.7 V 1 = 3.3 s tOFF = 1 - x 5V 200 kHz The timing capacitor can be calculated from the equation: CT = tOFF x I CT 3.3 s x 150 A = 150 pF VT (TH ) 3V (2) (1)
For 4 A peak-to-peak ripple current, which corresponds to approximately 25% of the 15 A full-load dc current in an inductor, Equation 4 yields an inductance of:
L= 1.7 V x 3.3 s = 1.4 H 4A
A 1.5 H inductor can be used, which gives a calculated ripple current of 3.8 A at no load. The inductor should not saturate at the peak current of 17 A and should be able to handle the sum of the power dissipation caused by the average current of 15 A in the winding and the core loss.
Designing an Inductor
Once the inductance is known, the next step is either to design an inductor or find a standard inductor that comes as close as possible to meeting the overall design goals. The first decision in designing the inductor is to choose the core material. There are several possibilities for providing low core loss at high frequencies. Two examples are the powder cores (e.g., Kool-M(R) from Magnetics, Inc.) and the gapped soft ferrite cores (e.g., 3F3 or 3F4 from Philips). Low frequency powdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low and the ripple current is high. Two main core types can be used in this application. Open magnetic loop types, such as beads, beads on leads, and rods and slugs, provide lower cost but do not have a focused magnetic field in the core. The radiated EMI from the distributed magnetic field may create problems with noise interference in the circuitry surrounding the inductor. Closed-loop types, such as pot cores, PQ, U, and E cores, or toroids, cost more, but have much better EMI/RFI performance. A good compromise between price and performance are cores with a toroidal shape.
The converter only operates at the nominal operating frequency at the above-specified VOUT and at light load. At higher values of VOUT, or under heavy load, the operating frequency decreases due to the parasitic voltage drops across the power devices. The actual minimum frequency at VOUT = 1.7 V is calculated to be 195 kHz (see Equation 3), where: RDS(ON)HSF is the resistance of the high-side MOSFET (estimated value: 14 m) RDS(ON)LSF is the resistance of the low-side MOSFET (estimated value: 6 m)
f MIN =
VIN - IO ( MAX ) x ( RDS (ON )HSF + RSENSE + RL ) - VOUT 1 x tOFF VIN - IO ( MAX ) x ( RDS (ON )HSF + RSENSE + RL - RDS (ON )LSF ))
(3)
REV. A
-7-
ADP3159/ADP3179
There are many useful references for quickly designing a power inductor. Table II gives some examples.
Table II. Magnetics Design References
Magnetic Designer Software Intusoft (http://www.intusoft.com) Designing Magnetic Components for High-Frequency DC-DC Converters McLyman, Kg Magnetics ISBN 1-883107-00-08
Selecting a Standard Inductor
The output ripple voltage can be factored into the calculation by summing the output ripple current with the maximum output current to determine an effective maximum dynamic current change. The remaining errors are summed separately according to the formula: VWIN = (V - VVID x 2 kVID ) x (5) IO 1 - IO + IO
2 k 2 2 2 kRCS + CSF + kRT + kEA = 95 mV 2
The companies listed in Table III can provide design consultation and deliver power inductors optimized for high power applications upon request.
Table III. Power Inductor Manufacturers
where kVID = 0.5% is the initial programmed voltage tolerance from the graph of TPC 6, k RCS = 2% is the tolerance of the current sense resistor, kCSF = 10% is the summed tolerance of the current sense filter components, kRT = 2% is the tolerance of the two termination resistors added at the COMP pin, and kEA = 8% accounts for the IC current loop gain tolerance including the gm tolerance. The remaining window is then divided by the maximum output current plus the ripple to determine the maximum allowed ESR and output resistance:
Coilcraft (847) 639-6400 http://www.coilcraft.com Coiltronics (561) 752-5000 http://www.coiltronics.com Sumida Electric Company (408) 982-9660 http://www.sumida.com
COUT Selection--Determining the ESR
RE ( MAX ) = ROUT ( MAX ) =
VWIN 95 mV = = 5 m IO + IO 15 A + 3.8 A
(6)
The output filter capacitor bank must have an ESR of less than 5 m. One can, for example, use five ZA series capacitors from Rubycon which would give an ESR of 4.8 m. Without ADOPT voltage positioning, the ESR would need to be less than 3 m, yielding a 50% increase to eight Rubycon output capacitors.
COUT --Checking the Capacitance
The required equivalent series resistance (ESR) and capacitance drive the selection of the type and quantity of the output capacitors. The ESR must be small enough to contain the voltage deviation caused by a maximum allowable CPU transient current within the specified voltage limits, giving consideration also to the output ripple and the regulation tolerance. The capacitance must be large enough that the voltage across the capacitor, which is the sum of the resistive and capacitive voltage deviations, does not deviate beyond the initial resistive deviation while the inductor current ramps up or down to the value corresponding to the new load current. The maximum allowed ESR also represents the maximum allowed output resistance, ROUT. The cumulative errors in the output voltage regulation cuts into the available regulation window, VWIN. When considering dynamic load regulation this relates directly to the ESR. When considering dc load regulation, this relates directly to the programmed output resistance of the power converter. Some error sources, such as initial voltage accuracy and ripple voltage, can be directly deducted from the available regulation window, while other error sources scale proportionally to the amount of voltage positioning used, which, for an optimal design, should utilize the maximum that the regulation window will allow. The error determination is a closed-loop calculation, but it can be closely approximated. To maintain a conservative design while avoiding an impractical design, various error sources should be considered and summed statistically.
As long as the capacitance of the output capacitor is above a critical value and the regulating loop is compensated with ADOPT, the actual value has no influence on the peak-to-peak deviation of the output voltage to a full step change in the load current. The critical capacitance can be calculated as follows: IO COUT ( CRIT ) = xL RE x VOUT (7) 15 A = x 1.5 H = 2.6 mF 5 m x 1.7 The critical capacitance for the five ZA series Rubycon capacitors is 2.6 mF while the equivalent capacitance is 5 mF. The capacitance is safely above the critical value.
RSENSE
The value of RSENSE is based on the maximum required output current. The current comparator of the ADP3159 has a minimum current limit threshold of 69 mV. Note that the 69 mV value cannot be used for the maximum specified nominal current, as headroom is needed for ripple current and tolerances.
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REV. A
ADP3159/ADP3179
The current comparator threshold sets the peak of the inductor current yielding a maximum output current, IO, which equals twice the peak inductor current value less half of the peak-topeak inductor ripple current. From this the maximum value of RSENSE is calculated as: The maximum duty ratio of the low-side (synchronous rectifier) MOSFET is:
DLSF ( MAX ) = 1 - DHSF ( MAX ) = 54%
(13)
The maximum rms current of the high-side MOSFET is:
IRMSHSF = DHSF ( MAX ) x IL ( VALLEY ) + ( IL ( VALLEY ) x IL ( PEAK ) ) + IL ( PEAK ) 3
2 2
RSENSE
VCS ( CL )( MIN ) 69 mV = = 4 m IL ( RIPPLE ) 15 A + 1.9 A IO + 2
(8)
IRMSHSF = 36% x
13.1 A2 + (13.1 A x 16.1 A ) + 16.1 A2 = 8.8 A rms 3
(14)
In this case, 4 m was chosen as the closest standard value. Once RSENSE has been chosen, the output current at the point where current limit is reached, IOUT(CL), can be calculated using the maximum current sense threshold of 87 mV:
The maximum rms current of the low-side MOSFET is:
IRMSLSF = DLSF ( MAX ) x IRMSLSF = 54% x IL ( VALLEY ) + IL ( VALLEY ) x IL ( PEAK ) + IL ( PEAK ) 3
2 2
IOUT ( CL ) =
VCS ( CL )( MAX ) IL ( RIPPLE ) - RSENSE 2 87 mV 3.8 A = - 20 A 4 m 2
13.1 A2 + (13.1 A x 16.1 A ) + 16.1 A2 = 10.8 A rms 3
(15)
(9)
The RDS(ON) for each MOSFET can be derived from the allowable dissipation. If 10% of the maximum output power is allowed for MOSFET dissipation, the total dissipation will be:
PD ( FETs ) = 0.1 x VOUT x IOUT ( MAX ) = 2 .26 W
At output voltages below 450 mV, the current sense threshold is reduced to 54 mV, and the ripple current is negligible. Therefore, at dead short the output current is reduced to:
(16)
IOUT ( SC ) =
54 mV = 13.5 A 4 m
(10)
Allocating half of the total dissipation for the high-side MOSFET and half for the low-side MOSFET and assuming that switching losses are small relative to the dc conduction losses, the required minimum MOSFET resistances will be: RDS (ON )HSF RDS (ON )LSF PHSF I HSF
2
To safely carry the current under maximum load conditions, the sense resistor must have a power rating of at least:
= =
1.13 W = 15 m 8 .8 A2 1.13 W = 10 m 10.8 A2
(17)
PRSENSE = ( IO )2 x RSENSE = (20 A )2 x 4 m = 1.6 W
Power MOSFETs
(11)
PLSF I LSF
2
(18)
Two external N-channel power MOSFETs must be selected for use with the ADP3159, one for the main switch and an identical one for the synchronous switch. The main selection parameters for the power MOSFETs are the threshold voltage (VGS(TH)) and the ON-resistance (RDS(ON)). The minimum input voltage dictates whether standard threshold or logic-level threshold MOSFETs must be used. For VIN > 8 V, standard threshold MOSFETs (VGS(TH) < 4 V) may be used. If VIN is expected to drop below 8 V, logic-level threshold MOSFETs (VGS(TH) < 2.5 V) are strongly recommended. Only logic-level MOSFETs with VGS ratings higher than the absolute maximum value of VCC should be used. The maximum output current IO(MAX) determines the RDS(ON) requirement for the two power MOSFETs. When the ADP3159 is operating in continuous mode, the simplifying assumption can be made that one of the two MOSFETs is always conducting the average load current. For VIN = 5 V and VOUT = 1.65 V, the maximum duty ratio of the high-side FET is:
DHSF ( MAX ) = 1 - ( f MIN x tOFF ) DHSF ( MAX ) = 1 - (195 kHz x 3.3 s ) = 36%
Note that there is a trade-off between converter efficiency and cost. Larger MOSFETs reduce the conduction losses and allow higher efficiency, but increase the system cost. If efficiency is not a major concern, a Vishay-Siliconix SUB45N03-13L (RDS(ON) = 10 m nominal, 16 m worst-case) for the high-side and a Vishay-Siliconix SUB75N03-07 (RDS(ON) = 6 m nominal, 10 m worst-case) for the low-side are good choices. The high-side MOSFET dissipation is:
PDHSF = I RMSHSF x RDS (ON ) + PDHSF VIN x I L ( PEAK ) x QG x f MIN 2 x IG (19) 5 V x 15 A x 70 nC x 195 kHz 2 = 8 .8 A x 16 m + = 1.75 W 2 x1 A
2
where the second term represents the turn-off loss of the MOSFET. In the second term, QG is the gate charge to be removed from the gate for turn-off and IG is the gate current. From the data sheet, QG is 70 nC and the gate drive current provided by the ADP3159 is about 1 A. The low-side MOSFET dissipation is:
PDLSF = IRMSLSF x RDS ( ON ) PDLSF = 10.8 A2 x 10 m = 1.08 W
2
(12)
(20)
Note that there are no switching losses in the low-side MOSFET.
REV. A
-9-
ADP3159/ADP3179
Surface mount MOSFETs are preferred in CPU core converter applications due to their ability to be handled by automatic assembly equipment. The TO-263 package offers the power handling of a TO-220 in a surface-mount package. However, this package still needs adequate copper area on the PCB to help move the heat away from the package. The junction temperature for a given area of 2-ounce copper can be approximated using: TJ = ( JA x PD ) + TA assuming: JA = 45C/W for 0.5 in2 JA = 36C/W for 1 in2 JA = 28C/W for 2 in2 For 1 in2 of copper area attached to each transistor and an ambient temperature of 50C: TJHSF = (36C/W x 1.48 W ) + 50C = 103C TJLSF = (36C/W x 1.08 W ) + 50C = 89C All of the above-calculated junction temperatures are safely below the 175C maximum specified junction temperature of the selected MOSFETs.
CIN Selection and Input Current di/dt Reduction
CH1 100mV CH2 M 250 s CH2 680mV
and this will produce an output voltage deviation equal to the ESR of the output capacitor array times the load current change.
TEK RUN: 200kS/s SAMPLE TRIG'D
(21)
2
Figure 4. Transient Response of the Circuit of Figure 3
100 90 80 70
EFFICIENCY - %
In continuous inductor-current mode, the source current of the high-side MOSFET is approximately a square wave with a duty ratio equal to VOUT/VIN and an amplitude of one-half of the maximum output current. To prevent large voltage transients, a low ESR input capacitor sized for the maximum rms current must be used. The maximum rms capacitor current is given by:
IC ( RMS ) = IO DHSF - DHSF = 15 A 0.36 - 0.362 = 7.2 A
2
60 50 40 30 20
(22)
10 0 0 2 4 6 8 10 12 14 OUTPUT CURRENT - A 16 18 20
For a ZA-type capacitor with 1000 F capacitance and 6.3 V voltage rating, the ESR is 24 m and the maximum allowable ripple current at 100 kHz is 2 A. At 105C, at least four such capacitors must be connected in parallel to handle the calculated ripple current. At 50C ambient, however, a higher ripple current can be tolerated, so three capacitors in parallel are adequate. The ripple voltage across the three paralleled capacitors is:
ESRC ( IN ) DHSF + VC ( IN )RIPPLE = IO x nC nC x CIN x f MAX 24 m 36% + VC ( IN )RIPPLE = 15 A x = 129 mV 3 x 1000 F x 195 kHz 3
Figure 5. Efficiency vs. Load Current of the Circuit of Figure 3
(23)
To further reduce the effect of the ripple voltage on the system supply voltage bus, and to reduce the input-current di/dt to below the recommended maximum of 0.1 A/ms, an additional small inductor (L > 1 H @ 10 A) should be inserted between the converter and the supply bus.
Feedback Compensation for Active Voltage Positioning
To correctly implement active voltage positioning, the low frequency output impedance (i.e., the output resistance) of the converter should be made equal to the maximum ESR of the output capacitor array. This can be achieved by having a singlepole roll-off of the voltage gain of the gm error amplifier, where the pole frequency coincides with the ESR zero of the output capacitor. A gain with single-pole roll-off requires that the gm amplifier output pin be terminated by the parallel combination of a resistor and capacitor. The required resistor value can be calculated from the equation:
RCOMP = ROGM x RTOTAL 1 M x 9.1 k = = 9.2 k ROGM - RTOTAL 1 M - 9.1 k
(24)
where:
RTOTAL =
Optimized compensation of the ADP3159 allows the best possible containment of the peak-to-peak output voltage deviation. Any practical switching power converter is inherently limited by the inductor in its output current slew rate to a value much less than the slew rate of the load. Therefore, any sudden change of load current will initially flow through the output capacitors,
nI x RSENSE 25 x 4 m = = 9.1 k gm x RE ( MAX ) 2 .2 mmho x 5 m
(25)
In Equations 24 and 25, ROGM is the internal resistance of the gm amplifier, nI is the division ratio from the output voltage to signal of the gm amplifier to the PWM comparator, and gm is the transconductance of the gm amplifier itself.
-10-
REV. A
ADP3159/ADP3179
Although a single termination resistor equal to RCOMP would yield the proper voltage positioning gain, the dc biasing of that resistor would determine how the regulation band is centered (i.e., offset). Note that sometimes the specified regulation band is asymmetrical with respect to the nominal VID voltage. With the ADP3159, the offset is already considered part of the design procedure--no special provision is required. To accomplish the dc biasing, it is simplest to use two resistors to terminate the gm amplifier output, with the lower resistor (RB) tied to ground and the upper resistor (RA) to the 12 V supply of the IC. The values of these resistors can be calculated using:
RA = VDIV 12 V = = 79.1 k gm x (VOUT (OS ) + K ) 2.2 mmho x (22 mV + 4.7 x 10-2 )
heavy loads where the voltage is "positioned" near one of the extremes of the regulation window rather than near the nominal center value. It must be noted and understood that this low gain characteristic (i.e., loose dc load regulation) is inherently required to allow improved transient containment (i.e., to achieve tighter ac load regulation). That is, the dc load regulation is intentionally sacrificed (but kept within specification) in order to minimize the number of capacitors required to contain the load transients produced by the CPU.
3.3V
ADP3159/ADP3179
(26)
VLR2 2.5V, 2.2A
1F
where K is a constant determined by internal characteristics of the ADP3159, peak-to-peak inductor current ripple (IRIPPLE), and the current sampling resistor (RSENSE). K can be calculated using Equations 28 and 29. VDIV is the resistor divider supply voltage (e.g., the recommended 12 V supply) and VOUT(OS) is the output voltage offset from the nominal VID-programmed value under no load condition. This offset is given by Equation 30. The closest 1% value for RA is 78.7 k. This value is then used to solve for RB:
RB = RA x RCOMP 78.7 k x 9.2 k = = 10.4 k RA - RCOMP 78.7 k - 9.2 k
1k RS 250m 68pF
LRDRV1
LRFB1 100 F 10k 2.5V
Figure 6. Adding Overcurrent Protection to the Linear Regulator
Linear Regulators
(27)
The nearest 1% value of 10.5 k was chosen for RB.
I x nI ) VGNL VCC (R K = L ( RIPPLE ) x SENSE - + gm x RTOTAL gm x RTOTAL 2 x gm ROGM 2 3.8 A 4 m x 25 1.174 12 V - x K = + 2 .2 mmho x 9.1 k 2 .2 mmho x 9.1 k 2 x 2 .2 mmho x 130 k 2 = 4.7 x 10
-2
(28)
The two linear regulators provide a low cost, convenient and versatile solution for generating additional supply rails. The maximum output load current is determined by the size and thermal impedance of the external N-channel power MOSFET that is placed in series with the supply. The output voltage is sensed at the LRFB pin and compared to an internal reference voltage in a negative feedback loop which keeps the output voltage in regulation. If the load is reduced or increased, the MOSFET drive will also be reduced or increased by the controller IC to provide a well-regulated 2.5% accurate output voltage. The LRFB threshholds of the ADP3159 are internally set at 2.5 V(LRFB1) and 1.8 V(LRFB2), while the LRFB pins of the ADP3179 are compared to an internal 1 V reference. This allows the use of an external resistor divider network to program the linear regulator output voltage. The correct resistor values for setting the output voltage of the linear regulators in the ADP3179 can be determined using:
VGNL = VGNLO + VGNL = 1V +
I L ( RIPPLE ) x RSENSE x nI VIN - VVID - x t D x RSENSE x nI L 2
3.8 A x 4 m x 25 5 V - 1.7 V - x 75 ns x 4 m x 25 = 1.174 V 2 1.5 H
(29)
VOUT (OS ) = (VOUT ( MAX ) - VVID ) - VOUT (OS )
RE ( MAX ) x I L ( RIPPLE ) - VVID x kVID 2 5 m x 3.8 A = 40 mV - - 1.7 V x 5 x 10-3 = 22 mV 2
(30)
VOUT(LR) = VLRFB x RU + RL RL
(32)
Finally, the compensating capacitance is determined from the equality of the pole frequency of the error amplifier gain and the zero frequency of the impedance of the output capacitor:
Assuming that RL =10 k, VOUT(LR) = 1.2 V and rearranging equation 32 to solve for RU yields:
COC
C x ESR 5 mF x 4.8 m = OUT = = 2 .6 nF RTOTAL 9.1 k
RU =
(31)
10 k x VOUT(LR) - VLRFB VLRFB
(
)
(33)
The closest standard value for COC is 2.7 nF
Trade-Offs Between DC Load Regulation and AC Load Regulation
RU =
10 k x (1.2V - 1V ) = 2 k 1V
Casual observation of the circuit operation--e.g., with a voltmeter --would make it appear that the dc load regulation appears to be rather poor compared to a conventional regulator (see Figure 4). This would be especially noticeable under very light or very
REV. A
-11-
ADP3159/ADP3179
Efficiency of the Linear Regulators LAYOUT AND COMPONENT PLACEMENT GUIDELINES
The efficiency and corresponding power dissipation of each of the linear regulators are not determined by the controller IC. Rather, these are a function of input and output voltage and load current. Efficiency is approximated by the formula:
The following guidelines are recommended for optimal performance of a switching regulator in a PC system:
General Recommendations
1.
V = 100% x OUT VIN
(34)
The corresponding power dissipation in the MOSFET, together with any resistance added in series from input to output, is given by: (35) PLDO = (VIN - VOUT ) x IOUT Minimum power dissipation and maximum efficiency are accomplished by choosing the lowest available input voltage that exceeds the desired output voltage. However, if the chosen input source is itself generated by a linear regulator, its power dissipation will be increased in proportion to the additional current it must now provide.
Implementing Current Limit for the Linear Regulators
For best results, a four-layer PCB is recommended. This should allow the needed versatility for control circuitry interconnections with optimal placement, a signal ground plane, power planes for both power ground and the input power (e.g., 5 V), and wide interconnection traces in the rest of the power delivery current paths. Whenever high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. If critical signal lines (including the voltage and current sense lines of the controller IC) must cross through power circuitry, it is best if a ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the cost of making signal ground a bit noisier. The GND pin of the controller IC should connect first to a ceramic bypass capacitor (on the VCC pin) and then into the power ground plane. However, the ground plane should not extend under other signal components, including the ADP3159 itself. The output capacitors should also be connected as closely as possible to the load (or connector) that receives the power (e.g., a microprocessor core). If the load is distributed, the capacitors should also be distributed, and generally in proportion to where the load tends to be more dynamic. It is also advised to keep the planar interconnection path short (i.e., have input and output capacitors close together). Absolutely avoid crossing any signal lines over the switching power path loop, described below. The switching power path should be routed on the PCB to encompass the smallest possible area in order to minimize radiated switching noise energy (i.e., EMI). Failure to take proper precaution often results in EMI problems for the entire PC system as well as noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors, the two FETs, and the power Schottky diode, if used, including all interconnecting PCB traces and planes. The use of short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause highenergy ringing, and it accommodates the high current demand with minimal voltage loss.
2.
3.
The circuit of Figure 6 gives an example of a current limit protection circuit that can be used in conjunction with the linear regulators. The output voltage is internally set by the LRFB pin. The value of the current sense resistor may be calculated as follows:
4.
RS
540 mV 540 mV = = 250 m IO ( MAX ) 2.2 A
(36) 5.
The power rating of the current sense resistor must be at least:
PD ( RS ) = RS x IO ( MAX ) = 1.2 W
2
(37)
The maximum linear regulator MOSFET junction temperature with a shorted output is:
TJ ( MAX ) = TA + ( JC x VIN x IO ( MAX ) ) TJ ( MAX ) = 50C + (1.4C / W x ( 3.3V x 2.2 A ) = 60C
(38)
6.
which is within the maximum allowed by the MOSFET's data sheet specification. The maximum MOSFET junction temperature at nominal output is:
TJ ( NOM ) = TA + ( JC x (VIN - VOUT ) x IO ( NOM ) ) TJ ( NOM ) = 50C + (1.4C / W x ( 3.3V - 2.5 V ) x 2 A ) = 52C
Power Circuitry
7.
(39)
This example assumes an infinite heatsink. The practical limitation will be based on the actual heatsink used.
-12-
REV. A
ADP3159/ADP3179
8. A power Schottky diode (1 ~ 2 A dc rating) placed from the lower MOSFET's source (anode) to drain (cathode) will help to minimize switching power dissipation in the upper MOSFET. In the absence of an effective Schottky diode, this dissipation occurs through the following sequence of switching events. The lower MOSFET turns off in advance of the upper MOSFET turning on (necessary to prevent cross-conduction). The circulating current in the power converter, no longer finding a path for current through the channel of the lower MOSFET, draws current through the inherent body-drain diode of the MOSFET. The upper MOSFET turns on, and the reverse recovery characteristic of the lower MOSFET's body-drain diode prevents the drain voltage from being pulled high quickly. The upper MOSFET then conducts very large current while it momentarily has a high voltage forced across it, which translates into added power dissipation in the upper MOSFET. The Schottky diode minimizes this problem by carrying a majority of the circulating current when the lower MOSFET is turned off, and by virtue of its essentially nonexistent reverse recovery time. Whenever a power-dissipating component (e.g., a power MOSFET) is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are: improved current rating through the vias (if it is a current path), and improved thermal performance-- especially if the vias extend to the opposite side of the PCB where a plane can more readily transfer the heat to the air. 10. The output power path, though not as critical as the switching power path, should also be routed to encompass a small area. The output power path is formed by the current path through the inductor, the current sensing resistor, the output capacitors, and back to the input capacitors. 11. For best EMI containment, the ground plane should extend fully under all the power components. These are: the input capacitors, the power MOSFETs and Schottky diode, the inductor, the current sense resistor, any snubbing elements that might be added to dampen ringing, and the output capacitors.
Signal Circuitry
9.
12. The output voltage is sensed and regulated between the GND pin (which connects to the signal ground plane) and the CS- pin. The output current is sensed (as a voltage) and regulated between the CS- pin and the CS+ pin. In order to avoid differential mode noise pickup in those sensed signals, their loop areas should be small. Thus the CS- trace should be routed atop the signal ground plane, and the CS+ and CS- traces should be routed as a closely coupled pair (CS+ should be over the signal ground plane as well). 13. The CS+ and CS- traces should be Kelvin-connected to the current sense resistor so that the additional voltage drop due to current flow on the PCB at the current sense resistor connections does not affect the sensed voltage. It is desirable to have the ADP3159 close to the output capacitor bank and not in the output power path, so that any voltage drop between the output capacitors and the GND pin is minimized, and voltage regulation is not compromised.
REV. A
-13-
ADP3159/ADP3179
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead TSSOP (RU-20)
0.260 (6.60) 0.252 (6.40)
20
11
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
1 10
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
SEATING PLANE
0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
8 0
0.028 (0.70) 0.020 (0.50)
-14-
REV. A
ADP3159/ADP3179 Revision History
Location Global change from ADP3159 to ADP3159/ADP3179 Data Sheet changed from REV. 0 to REV. A. Page
Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Addition to LINEAR REGULATORS section of the SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edit to ERROR AMPLIFIER section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Addition to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edits to the On-board Linear Regulator Controllers section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Edits to Equation 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Edits to Feedback Compensation for Active Voltage Positioning section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Edit to Equation 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Addition of new text to Linear Regulators section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
REV. A
-15-
-16-
C02190-1-7/01(A)
PRINTED IN U.S.A.
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